Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common and important semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily-doped source/drain regions 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO.sub.2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
The source/drain regions 105, illustrated in FIG. 1, are lightly-doped-drain (LDD) structures. Each LDD structure includes a lightly-doped, lower conductivity region 106 near the channel region 107 and a heavily-doped, higher conductivity region 104 typically connected to the source/drain terminal. Generally, the LDD structures are typically formed by: implanting a first dopant into active regions adjacent the gate electrode 103 at relatively low concentration levels to form the lightly-doped regions 106; forming spacers 108 on sidewalls of the gate electrode 103; and implanting a second dopant into the active regions at higher concentration levels to form the heavily-doped regions 104. The substrate is typically annealed to drive the dopant in the heavily-doped regions deeper into the substrate 106.
After the LDD structures have been formed, a relatively thick oxide layer (not shown), referred to as a contact formation layer, is disposed over the substrate 101. Openings are generally cut into the contact formation layer to expose the source/drain regions 105 and the surface of the gate electrode 103. The exposed areas are then filled with a metal, such as tungsten, which is used to connect the active elements with other devices on the chip.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region 107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral and vertical dimensions of the device structure.
The depth and extent of lateral diffusion of the LDD region are important dimensions which must be scaled down as the device structure is made smaller. Lateral diffusion of the dopant used to form the LDD region shortens the effective length of the channel region and consequently limits the ability to scale down the semiconductor device. Lateral diffusion of the LDD region dopant often occurs during processing in fabrication steps subsequent to LDD region formation, including the annealing step used to drive-in the dopants of the heavily-doped, higher conductivity region. A more detailed description of LDD structures and the fabrication thereof may be found in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 354-363 and 436-439.